ceClub: NAND Flash Architectures Reducing Write Amplification through Multi-Write Codes

Saher Odeh (Technion)
Wednesday, 31.12.2014, 11:30
EE Meyer Building 861

Multi-write codes hold great promise to reduce write-amplification in flash-based storage devices. In this talk we propose two novel mapping architectures that show clear advantage over known schemes using multi-write codes, and over schemes not using such codes. To evaluate the performance gain we use industry-accepted benchmark traces, as well as synthetically-generated workloads with time locality. The results show write-amplification savings of double-digit percentages, for as low as 10% over-provisioning. In addition, we discuss an analytic model that accurately predicts the write-amplification given parameters describing both the device and the workload.

Saher Odeh finished his BSc degree at the Computer Science faculty of the Technion, and is now completing his MSc degree at the Electrical Engineering faculty of the Technion (advised by Prof. Yuval Cassuto). In parallel, he is working at the Intel Corporation as Back-End integration systems engineer. His areas of interests are storage and distributed systems architecture.

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