TCE Guest Lecture: Sensing CPU Electro-Magnetic Emanations for Voltage Noise Characterization

Yanos Sazeides (University of Cyprus)
Tuesday, 5.12.2017, 11:30
EE Meyer Building 1061

A combination of supply-voltage scaling, GHz+ operating frequencies and multi-core execution makes power-delivery a critical challenge for high-end processing systems. Previous work on Power-Delivery Network monitoring approaches consume expensive pad resources or suffer from design-time and run-time overheads. In this talk, we present a non-intrusive power delivery network monitoring methodology based on sensing modulations in the emanated CPU electromagnetic radiation due to dynamic code-execution. We demonstrate that using this methodology it is possible to a) detect large power-supply oscillations that are directly correlated with voltage-noise emergencies, b) drive a genetic-algorithm framework to automatically generate voltage noise (dI/dt) stress tests based on electromagnetic signal amplitude feedback and c) obtain the first-order resonance-frequency of the power delivery network LC-tank network. The generality of the approach is established by successfully using it on three different CPUs: two ARM multi-core CPU clusters hosted on in a big.LITTLE configuration and an x86-64 AMD desktop CPU. The efficacy of the proposed methodology is validated through Vmin and direct voltage noise measurements. This talk is based on a recently accepted paper at Computer Architecture Letters and the authors of the paper are Zacharias Hadjilambrou (U Cyprus), Shidhartha Das (ARM), Marco Antoniades (U Cyprus) and Yiannakis Sazeides (U Cyprus). This work is partially supported by European Union Horizon 2020 project Uniserver grant no. 688540 and the University of Cyprus.

Yiannakis (Yanos) Sazeides is an Associate Professor at the University of Cyprus. He was awarded a PhD from the University of Wisconsin-Madison in 1999. He has worked at Compaq and Intel where he contributed to the development and design of high performance processors. His research interests lie in the area of Computer Architecture with particular emphasis on reliability, memory hierarchy, data center modelling, and analysis of dynamic program behavior.

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