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PartTLB: Dynamic TLB Partitioning for SMT Systems
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Maxim Barsky, M.Sc. Thesis Seminar
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Thursday, 10.3.2022, 15:30
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Zoom Lecture: 93840198625
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Advisor:  Prof. D. Tsafrir
Simultaneous multithreading (SMT) increases the cost of memory address translation due to sharing of the translation lookaside buffer (TLB) among multiple threads. Current x86 processors use a ``competitively-shared’’ TLB, in which low-locality threads might needlessly waste TLB resources and thus degrade the performance of neighboring high-locality threads. To address this problem, we introduce PartTLB, a new mechanism that: (1) samples the TLB requests of the competing threads, (2) predicts their miss rate with different TLB sizes, and (3) partitions the TLB accordingly to minimize the overall miss rate. PartTLB requires small additional hardware (about 1% of the TLB size) and no software involvement. For a 2-way SMT, PartTLB improves performance by up to 37% for one thread and worsens performance by up to 3% for the other thread.
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