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Model-Based Simulation for SMT Cores
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Idan Raz, M.Sc. Thesis Seminar
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Thursday, 10.3.2022, 14:30
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Zoom Lecture: 91575675908
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Advisor:  Prof. D. Tsafrir
Studies that evaluate new architectural designs of virtual memory typically employ a ``model-based’’ methodology that relies on simulations of the translation lookaside buffer (TLB) coupled with empirical performance models. We observe that this methodology is limited in that each simulated thread of execution has its own dedicated TLB, whereas modern processors share a single TLB among multiple threads through ``simultaneous multithreading’’ (SMT). Existing model-based research is thus unable to explore virtual memory designs in SMT context. We address this problem: (1) by showing that the behavior of different multiprogrammed thread combinations varies over time nontrivially, and by introducing a systematic approach for measuring this behavior with bounded error; (2) by developing a TLB simulator capable of realistically combining multiple memory-reference streams (of the SMT threads) into one; (3) by validating the simulator’s accuracy against real (Intel) processors to ensure the correctness of our approach, which required us to reverse engineer their TLB eviction policy; and (4) by showing how to build empirical models that predict runtimes of different SMT combinations from their combined simulated TLB miss rate. We demonstrate our methodology’s usefulness by evaluating a new TLB partitioning mechanism for SMT processor cores.
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