אירועים

The traditional performance-cost benefits enjoyed for decades from scaling of device area are challenged by the slowdown of voltage scaling and less reliable silicon primitives. These developments lead to pessimistic projections that it will be impossible to operate all on-chip resources, even at the minimum voltage for safe operation, due to power constraints, and the growing design and operational margins, used to provide silicon primitives with resiliency against variations, will consume the scaling benefits.

Our attempt, presented in this talk, towards reversing these negative trends is a first-order model that determines analytically the performance degradation due to permanently faulty cells in processor arrays. We refer to this degradation as the performance-vulnerability-factor (PVF). The study assumes a future where cache blocks with faulty cells are disabled resulting in less cache capacity and extra misses, while faulty predictor cells are still used but cause additional mispredictions. The model, for a given program run, random probability of permanent cell failure, and processor configuration, can provide rapidly an assessment of the expected PVF as well as lower and upper PVF probability distribution bounds for an individual or combination of arrays.

Bio
Yiannakis Sazeides is an Associate Professor at the University of Cyprus. He was awarded a PhD from the University of Wisconsin-Madison in 1999. He worked at Compaq and Intel towards the development and design of high performance processors. His research interests lie in the area of Computer Architecture with particular emphasis on reliability, memory hierarchy, data center modelling, and analysis of dynamic program behavior.