אירועים והרצאות בפקולטה למדעי המחשב ע"ש הנרי ומרילין טאוב

The virtual memory subsystem translates the address of each memory reference from its virtual to its physical representation, increasing execution runtimes by as much as 50% and 90% in bare-metal and virtual setups, respectively. We alleviate these overheads by developing improved virtual memory designs: (i) hashed page tables and (ii) TLB partitioning for simultaneous multithreading. We additionally develop an efficient and reliable methodology for evaluating the performance of newly proposed virtual memory designs, replacing conventional full-system, cycle-level simulations with much faster partial simulations of only the virtual memory subsystem, whose outputs are fed into a mathematical model that predicts the execution runtime.