Hardware Reverse Engineering (HRE) involves gate-level Netlist extraction and specification discovery, wherein graph-based methods play a crucial role in identifying sub-circuits. We propose a novel approach for Subcircuit Recognition, essential for specification discovery in HRE, leveraging existing graph similarity kernels. Focusing on the reduced problem we formulate as Subgraph Localization, we delineate two key components: graph similarity metric and graph adjacency mask inference, crucial for accurately locating subgraphs amidst complex circuit representations. Due to the dearth of domain examples, traditional supervised learning methods prove inadequate, prompting the formulation of a self-supervised approach tailored to the unique challenges of the circuit identification problem. Our contributions encompass the exploration of a novel Netlist graph representation, the formulation of an end-to-end learnable subgraph localization scheme, and the development of a comprehensive framework for evaluating graph similarity methods in this context. Moreover, we present techniques for overcoming challenges such as lack of labels and matching non-isomorphic subgraphs.
